sub-computer organization b.tech 2nd year cse

Uttarakhand Technical University

(utu)

B.tech (2nd year)

2012 Examination

sub:- Computer Organization

time:- 3hr

total marks :100

Note : Attempt all the questions.

Q1:- Attempt any four parts of the following :

1. What to you mean by inter-register transfer? Discuss Bus transfer.
2. Design Arithmetic Logic Shift unit that will perform different arithmetic, logic an shift operation.
3. Draw a diagram of bus system for four register of 4-bits each. The bus is to be constructed with multiplexers.
4. Show the hardware implementation for the following statements. The registers are 4-bits in lengths :
   TO : A RO
   T1  : A  R1
   T2  : A  R2
   T3  : A  R3
5. Show the multiplication process using Booth's algorithm when the following binary numbers are multiplied : (12)*(-18)
6. Represent the decimal number -0.654 into IEEE Floating point format.

Q2:- Attempt any Four parts of the following :

1. Explain the Fetch and Execute cycle during execution of an instruction.
2. Describe briefly a Hardwired Control.
3. What is microinstruction? Describe the microinstruction format.
4. What do you mean by the term Microprogram Sequence. Explain the role played by it.
5. Discuss advantages and disadvantages of Micro-programmed Control.
6. Explain wide-branch addressing and emulation.

Q3 Attempt any two parts of the following :

1. Write a program to evaluate the arithmetic expression :
   X= (A+B*C)/(D+E*F/G+H) Using three, two, one and zero address Instructions.
2. Design an efficient logic circuit shared by different branch condition derived form the combination or stand alone status of the Flag register bits S (sign), V(overflow), C(End carry), Z(all O's). Specific the conditional branch instruction which can b supported by the circuit you have designed.
3. Describe DMA with suitable blocks diagram. Why does DMA have priority over the CPU when both request a memory transfer ? Explain,

Q4:- Attempt any two parts of the following :

1. The access time of a cache memory is 100 ns and that of main memory 1000 ns. It is estimated that 80 percent, of the memory requests are for read and the remaining 20 % for write. The hit ratio for read accesses only is 0.9.
   (a) What is the average access time of the system considering only memory read cycles ?
   (b) What is the average access time of the system for both read and write requests ?
   (c) What is the hit ratio taking into consideration the write cycles ?
2. A Block set associative cache consists of a total of 64 blocks divided into four block sets. The main memory containing 4096 blocks each consisting of 128 words.
   (a) How many bits are there in the main memory address ?
   (b) How many bits are there in each of TAG, SET and WORD field ?
3. Discuss the concept and implementation of virtual memory. Also describe a suitable scheme for translation from logical address to physical address.

Q5:- Attempt any two parts of the following :

1. Give various architectural classification schemes. Also discuss the Flynn's and Feng's Classification in detail.
2. Discuss the various possible hazards between read and write operations in an instruction pipeline and state the mechanism to detect and avoid these hazards. Also discuss the dynamic instruction scheduling.
3. Consider the execution of  a program of 15000 instructions by a linear pipeline processor with a clock rate of 25 MHz. Assume that the instruction pipeline has five stages and that one instruction and out of sequence executions are ignored.
   (a) Calculate the speedup factor in using this pipeline to execute the program as compared with the use of an equivalent nonpipelined processor with an equal amount of flow through delay.

-------------------

this question paper is only for Uttarakhand techinical university (UTU).Step4success is the only ultimate collection of question papers of UTU and HNB.

Best of luck guys :)