Fundamental of Electronics Engineering B.Tech UTU PREVIOUS YEAR QUS PAPER 1st YEAR (I SEM)

Uttarakhand Technical University
B.tech (first year)

odd sem Examination

2009-10

sub :- Fundamental of Electronics

Engineering

time : 3hr] 

Total marks :100

SECTION A

Q1:- Attempt any four of the following :

4x5=20

1. What is Fermi Level? How this level is modified when we add
   (a) P-type
   (b) n-type impurity to the intrinsic semiconductor.
2. Calculate the barrier potential at room temperature for p-n junction is silicon, which is doped to a carrier density 10²²  m^-3 of on the p-side and 22²² m^-3 on the n-side. The intrinsic carrier density for silicon is 1.4 × 10¹⁶ m^-3.
3. Explain the following:
   (a) Transition capacitance
   (b) Diffusion capacitance
   (c) Diode resistance
4. Describe the bridge rectifier. How does it differ from F.W. rectifier using two diodes only. What do you understand by PIV?
5. Calculate the ripple factor and conversion efficiency of half wave rectifier.
6. A full wave rectifier delivers 50 W to a load of 200 ohm. If the ripple factor is 1%. Calculate AC ripple voltage across the load.

SECTION B

Q2:- Attempt any four of the following:

4x5=20

1. Explain roll of base in npn transistor and its effect on emitter and base currents.
2. Draw a positive and a negative clamper circuit and draw the input and output waveform.
3. Differentiate between Avalanche and Zener breakdown mechanism. What is the effect of increasing temperature on the breakdown voltage in each case?
4. For the voltage circuit in fig. determine the maximum and minimum 
   I_z.
   
   

   

   UTU Fig. 1

   
   
   
5. In an n-p-n transistor (Si), α = 0.975, I_E  = 10 mA, Calculate value of
   (a) β
   (b) g_m
   (c) I_{c
   (d)} I_B
6. Explain how MOSEFT can be used as a voltage variable resistor.

SECTION C

Q3:- Attempt any two of the following:

10x2=20

1. Determine and plot the output voltage for the circuit shown in fig.
2. What is the purpose of biasing the transistor? Explain various biasing arrangements used.
   

   

   Assume all the diodes as ideal.
   UTU Fig.2

   
   
   
   
   
   
3. Explain the input and output characteristics of transistors in common emitter configuration. 

SECTION D

Q4:- Attempt any two of the following:

10X2=20

1. What is the difference between depletion and enhancement type MOSEFT in terms of construction, operation and characteristics.
2. Design a JFET circuit with voltage divider biasing circuit (refer Fig.) with transistor parameter I_Dss = 100kΩ. Design the circuit such the circuit such that DC drain current is I_D = 5mA and dc drain to source voltage is V_DS = 5V.

   

   UTU Fig.3

     
3. Define the drain resistance, the transconductance and amplification factor of JFET. Explain what is pinch off JFET.

SECTION E 

Q5:- Attempt any two of the following:

10X2=20

1. (a) Realize an XOR gate using only NAND gates
   (b) What is Demorgan's theorem?
   (c) How many different functions may be realized with n variables?
   (d) Convert (72)₁₀ into hexadecimal number.
2. Explain the characteristics of ideal operation amplifier. How it can be used for realizing the adder circuit?
3. Design an inverting a non-inverting amplifier using OPAMP. 

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BEST OF LUCK!!