vlsi technology
SEM V, 2011-12
B.TECH
previous year question papers
UTTARaKHAND TECH. UNIVERSITY (UTU)
Time: 3 hours
Total
marks :100
Attempt any four parts
of the following:
- Discuss different steps in preparing wafers from raw
silicon.
- A silicon ingot with 0.5 x 1016 boron
atoms/cm3 is to be grown by CZ method. What should be the
concentration of Boron in the melt to obtain the required doping
concentration? The segregation coefficient of boron is 0.8.
- Explain the application of SiO2 layer
in IC fabrication.
- Show that to grow an oxide layer of thickness x, a
thickness of 0.44 x of silicon is consumed.
- Explain briefly features size, chips, wafers,hybrid and
monolithic circuits.
- State Moore's law and explain the deviation from the
predicated path.
Attempt any four parts:
- If the measured phosphorous profile is represented by a
Gaussian function with a diffusivity D =2.3 x 10-13 cm2/s,
and the measured junction depth is 1 x 1018 atoms/cm2and the
measured junction depth is 1μm at a substrate concentration of
1 x 1015 atoms/cm3. Calculate the diffusion
time.
- Describe a typical ion implanter. What are the
advantages of ion implantation?
- Explain vapor phase epitaxy and also tell what are the
sources of silicon in vapour phase epitaxy.
- Compare ion implantation process with diffusion.
- What do you mean by annealing and why it is required in
IC fabrication process.
- Explain solid source diffusion of Boron.
Attempt any four parts:
- List the defects in pattern transfer.
- List all process steps of pattern transfer with
diagram.
- What are PR materials? Describe all types of PR. What
are the properties of good PR?
- Explain proximity printing and projection printing and
compares these two.
- Explain all properties of etchant.
- Explain ion beam lithography process.
Attempt any Two parts:
- Give the various fabrication steps of npn transistor
with diagram and brief explanation.
- Explain the metallization and also describe the
problems associated with the process. Explain dc sputtering method of
metallization.
- Give the various fabrication steps of CMOS transistor
using n well technique with diagram and brief explanation.
Attempt two parts:
- Write a short note on Package types and packaging
design VLSI technology. What is meant by DIP?
- Write a detailed note on different yield loss
mechanisms in VLSI.
- Explain why modeling of yield loss mechanisms is
required. Explain general model of yield loss mechanism and also explain
accelerated testing in brief.
-----------------------utu previous year question papers of B.tech, Bba, B.com, B.sc and Mba old year question papers Uttarakhand technical University (UTU)---------------------------
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